1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a semiconductor chip and a resin sealing portion.
2. Description of the Background Art
As a semiconductor device for use as an inverter, there is a power module having a plurality of semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and free wheel diodes sealed with a mold resin and an insulating sheet. For example, Japanese Patent Laying-Open No. 2006-319084 discloses such a power module.
As an art for downsizing a semiconductor device sealed with a resin, there is an art disclosed in Japanese Patent Laying-Open No. 2003-007966, for example. According to this art, a semiconductor device includes a radiation substrate, a semiconductor element provided on this radiation substrate, a plurality of main electrode plates having respective one ends electrically connected to a main electrode of the semiconductor element, and a resin package for sealing the radiation substrate, the semiconductor element and the plurality of main electrode plates with a resin. The respective other ends of the plurality of main electrode plates are exposed to the outside on the upper surface side of the resin package. The resin package is integrally formed by a molding method.
In the art disclosed in foregoing Japanese Patent Laying-Open No. 2003-007966, the electrode on the surface of the semiconductor chip and the main electrode plate are connected by wire bonding. Therefore, a region required for the wire bonding must be ensured and it is difficult to further downsize the semiconductor device. Furthermore, for example, a special die is required to allow the main electrode to project from the surface of the resin package (the upper surface side) directly on the surface of the semiconductor chip, which leads to a rise in manufacturing costs.